Integrated circuit chips comprise semiconductor devices formed on a substrate such as a semiconductor wafer and include metalized contact, or attachment, pads for providing an electrical interface to the integrated circuitry. Conventional techniques for providing a connection between the internal circuitry of a chip and external circuitry, such as a circuit board, another chip, or a wafer, include wire bonding, in which wires are used to connect the chip contact pads to the external circuitry, and may also include other techniques known in the art. A more recent chip connection technique, known as flip chip technology, provides for connection of integrated circuit devices to external circuitry using solder bumps that have been deposited onto the chip contact pads. In order to mount the chip to external circuitry, the chip is flipped over so that its top side faces down and its contact pads are aligned with matching contact pads on the external circuit. The solder is then flowed between the flipped chip and the substrate supporting the external circuitry to complete the interconnect. The resulting flip chip package is much smaller than a traditional carrier-based system, because the chip is positioned directly on the external circuitry, such that the interconnect wires may be much shorter. As a result, the inductance and resistive heat are greatly reduced, enabling higher-speed devices.
Recent trends in high-density flip chip interconnects have led to the use of circular copper pillar bumps for central processing unit (CPU) and graphics processing unit (GPU) packaging. Copper pillar bumps are attractive replacements for traditional solder bumps, but circular copper pillar bumps have several disadvantages. For example, circular shaped copper pillar bumps add significant size to the interconnect structure, thereby limiting the pitch dimension of metal trace lines for the interconnect. As a result, the current circular shaped bumps will eventually become a bottleneck to the continuous device shrinking in the integrated circuit (IC) industry. Another disadvantage to circular copper pillar bumps is the mechanical stress created at the packaging circuitry as well as the underlying layers due to mismatched thermal expansion of the chip and the packaging structure. It has been observed that the stress at the edge of under-bump metallization (UBM) layer is very high after packaging, and thus the induced stress force causes dielectric layer delamination particularly critical in circuitry having extra low-k (ELK) dielectric layers, as the k value is lower than 3. The packaging structure therefore becomes more and more fragile. In addition, the large electrical current density at the circular bump-to-pad interface contributes to electromigration and electric stress. Examples of types of damage from electromigration include micro-racking in solder joints and delamination in bonding layers.